1. Field
The disclosure relates generally to computer modeling of chip designs and more specifically to determination of resistance and parasitic capacitance by Design Automation Software Applications.
2. Description of the Related Art
Wire shapes in a wiring layout are defined with a certain width by the designer. However, due to modern chip fabrication processes, these widths do not always reflect the width of the actual wire after fabrication. This variance between design and fabrication width is referred to as width bias. The width bias, of a wire fabricated on a chip with the latest small wire geometry, has become dependent on the spacing to neighboring wires. In order to validate a design to the design specification, electrical values, such as parasitic capacitance and resistance values, must be calculated each time a change is made to a wiring layout.
In order to accurately calculate parasitic capacitance and resistance values, Design Automated Software Applications (DA applications) must correct for this width bias. In particular, those DA applications that extract electrical parasitic values often require large amounts of memory and processor resources because many of the calculations performed require design context data to account for contextually sensitive width biasing. An example of contextually sensitive width biasing can be seen in regard to isolated wires. CATastrophic Optical Proximity Correction (CATOPC), a DA application, widens isolated wires to make them easier to print. Therefore, isolated wires have more width variability than wires that are not isolated. The width variability caused by the widening requires calculations to account for the resulting width biasing. A known method to process contextually sensitive biasing is to store the effects by edge, rather than by wire. However, this method requires double the memory.
Each DA application modification to wiring creates a requirement for new biasing calculations. When the resistance or capacitance of a wire shape is affected by neighboring wire shapes so that performance of the wire shape is not within the required limits, a DA application adjusts the width of the wire shape to change the resistance or capacitance due to the neighboring wire shapes. Additionally, when the proximity of one wire to another could cause a short, the DA application adjusts the location of the wire to prevent the short. Each time the resistance or capacitance changes due to a bias, a DA application must determine the new electrical values in order to validate a design specification. DA applications can cause the bias of a wire shape to be a function of the distance to its neighbor on the same metal level. As a result, a particular wire shape segment may have several biasing variations along its length. The several biasing variations along the length are not necessarily aligned on the two sides of the wire shape. Furthermore, there may be a width-dependent bias that is applied after spacing-dependent biases are applied, implying that the bias on both sides must be known before the width-dependent bias can be determined. When the bias on both sides must be known before the width-dependent bias can be determined, the neighboring shapes on both sides of the wire shape must be known in order to determine the width of the wire shape prior to determining the processing bias.
In particular, this is the case for DA applications that examine the shapes of a design with a “scanline”. A scanline is a line that sweeps from one side of the chip design to the other. As the scanline sweeps from one side of the chip design to the other, it identifies each wiring shape as it contacts each wiring shape. Therefore, a DA application employing a scanline can determine only one of the two possible distances to neighbors of a wire shape at any one time. To accurately determine the complete bias as discussed above, the spacing-dependent bias of both sides must be simultaneously known. Determining the spacing to one side and saving the spacing dependent bias for that side until the spacing to the other side is determined, creates a problem. The problem is that it may be too late for the DA application to calculate capacitance to the first neighboring shape because the first neighboring shape has been lost due to the examination process. Because of this effect, DA applications must consume considerable storage remembering the important information and sustain a performance loss organizing that information.
Therefore, a need exists for a way to reduce memory and performance consumption when calculating parametric electrical values due to width bias for design validation.